There are a number of conventional processes for packaging integrated circuits. Many packaging techniques use a leadframe that has been stamped or etched from a metal (typically copper) sheet to provide electrical interconnects to external devices. One relatively recently developed packaging style is a leadless leadframe package (LLP) (also referred to as a quad flat pack—no leads (QFN) package). In a leadless leadframe package, the leadframe typically includes an array of contacts that are exposed on the bottom surface of the package. The LLP may also include lead traces that may or may not be exposed at the bottom surface of the package.
A die mounted on the leadframe is wire bonded (or otherwise electrically connected) to the contacts and/or the lead traces, the lead traces serving as electrical connectors between the bonding wires and associated contacts. Often the LLP will have a die support structure upon which the die is mounted. After the dice are attached to the leadframe panel, an encapsulant material is often used to encapsulate the entire device area including the die, wire bonds, contacts and/or lead traces such that the encapsulated structures remain rigidly fixed.
A notable advantage of such an LLP arrangement is that the integrated circuit device package can be made to have a substantially smaller footprint than that obtainable with conventional leadframes.
LLP packages in general have generated a great deal of interest within the semiconductor industry. Although existing techniques for fabricating LLPs and for packaging integrated circuits using LLP technology work well, there are continuing efforts to develop even more efficient designs and methods for packaging integrated circuits.